As is known in the art, network devices, such as routers and switches, can include network processors to facilitate receiving and transmitting data. In certain network processors, such as IXP Network Processors by Intel Corporation, high-speed queuing and FIFO (First In First Out) structures are supported by a descriptor structure that utilizes pointers to memory. U.S. Patent Application Publication No. US 2003/0140196 A1 discloses exemplary queue control data structures. Packet descriptors that are addressed by pointer structures may be 32-bits or less, for example.
In one known configuration, queues are controlled by a queue descriptor data structure that includes a head pointer for the address of first element of the list and a tail pointer for the address of the last element of the list. Ring structures are controlled by an analogous ring descriptor data structure having a remove pointer and an insert pointer. Maintaining efficient access to the queue descriptors and ring descriptors is challenging when the number of queues/rings becomes relatively large (e.g., 500,000 to 1,000,000 queues/rings).